The present invention relates to a control circuit for semiconductor memory device, more particularly to a control circuit capable of reducing power consumption by controlling WRITE operation of SRAM (Static Random Access Memory).
Generally, SRAM memory cell includes a flip-flop circuit for data storage and two switch elements (e.g. two access transistors). In SRAM, if the access transistors are applied with a pulse through a word line so that the cell transistor is turned on, access for data writing or reading to/from the memory cell can be made. In addition, if the write signal is active (e.g. "high" level), data transfer can be made between a pair of bit lines and a pair of data bus lines.
In addition, the data of SRAM is statically maintained to a cell without any refresh operation due to the feedback effect of the flip-flop included therein, as long as the power is supplied thereto. This is contrary to that of DRAM.
FIG.1 is a circuit diagram illustrating a conventional SRAM of a semiconductor memory device, which includes a dummy bit line unit.
Referring to FIG. 1, the reference character 60 represents the dummy bit line unit and the reference character 80 represents a memory circuit unit (e.g. SRAM circuit unit) including memory cell array. The SRAM circuit unit 80 includes NMOS transistors NM1 and NM2 for bit line precharging, NMOS transistors NM3 and NM4 for bit line static precharging, a plurality of memory cells 10, NMOS transistors NM5 and NM6 for column selecting, and a sense amplifier 20. Each of the NMOS transistors NM1 and NM2 has a gate applied with a precharge signal PRE. Thus, the NMOS transistors NM1 and NM2 are turned on by the high level of the precharge signal PRE, which in turn, precharge the bit line BL and the inverted bit line /BL, respectively. The static precharge NMOS transistor NM3 is diode-coupled from the power signal VDD to the bit line BL and the static precharge NMOS transistor NM4 is diode-coupled from the power signal VDD to the inverted bit line /BL. The memory cell 10 is coupled between the bit line BL and the inverted bit line /BL. Each of the NMOS transistors NM5 and NM6 has a gate applied with a column signal COL for selecting the bit line and the inverted bit line /BL, respectively. The sense amplifier 20 is coupled between a data bus line DBL and an inverted data bus line /DBL and is activated by a sense enable signal SE to sense and amplify the data.
The dummy bit line unit 60 of FIG. 1 produce an inverted dummy bit line signal /S1 in response to the precharge signal PRE from an address signal transition detector (see FIG. 2) and a plurality of word line signals WL [M-1:0] from a word line signal generator (not shown). The dummy bit line unit 60 comprises an NMOS transistor NM62 whose drain-source path is coupled between the power voltage VDD and the dummy bit line DUBL and whose gate is applied with the precharge signal PRE; a plurality of NMOS transistors NM64, NM66 and NM68 each drain-source path being coupled between the dummy bit line DUBL and the ground and each gate being applied with the corresponding word line signal WL[M-1:0], respectively; and an inverter IV62 whose input is coupled to the dummy bit line DUBL for producing the inverted dummy bit line signal /S1.
In addition, the memory cell array of conventional SRAM further includes NMOS transistors NM7 and NM8 for write operation, two CMOS inverters 30 and 40. Each of the NMOS transistors NM7 and NM8 has a gate applied with an internal write signal WR and is activated the high level of the write signal WR, that is the duration for write operation. The CMOS inverter 30 includes a PMOS transistor PM1 and an NMOS transistor NM9 coupled, in series, between the power voltage VDD and ground VSS. Also, the output of the CMOS inverter 30 is coupled to the drain of NMOS transistor NM8 and the input thereof is coupled for receiving a data input signal DIN. The CMOS inverter 40 includes a PMOS transistor PM2 and an NMOS transistor NM10 coupled in series, between the power voltage VDD and ground VSS. Also, the input of the CMOS inverter 40 is coupled to the output of the CMOS inverter 30 and the output thereof is coupled to the drain of the NMOS transistor NM7.
In the meantime, the bit line BL is coupled between the NMOS transistor NM1 for bit line precharge and the NMOS transistor NM5 for selecting a column, while the inverted bit line /BL is coupled between the NMOS transistor NM2 for precharging and the NMOS transistor NM6 for selecting. The data bus line DBL is coupled between the NMOS transistor NM5 for selecting and the NMOS transistor NM7 for writing, while the inverted data bus line /DBL is coupled between the NMOS transistor NM6 for selecting and the NMOS transistor NM8 for writing.
The memory cell 10 includes two PMOS transistors PM3 and PM4, and four NMOS transistors NM11, NM12, NM13 and NM14. The memory cell 10 further includes two storage nodes N1 and N2. The PMOS transistor PM3, the storage node N1 and the NMOS transistor NM11, are coupled in series, between the power voltage VDD and the ground VSS. Likewise, the PMOS transistor PM4, the storage node N2 and the NMOS transistor NM12, are coupled in series, between the power voltage VDD and the ground VSS. For the NMOS access transistor NM13, the gate thereof is coupled to the corresponding word line WL and the source-drain path thereof is coupled between the storage node N1 and the bit line BL. Also, for the NMOS access transistor NM14, it's gate is coupled to the word line WL and it's source-drain path is coupled between the storage node N2 and the inverted bit line /BL.
In addition, in the memory cell 10, the gates of the PMOS transistor PM3 and the NMOS transistor NM11 are coupled to the storage node N2, while the gates of the PMOS transistor PM4 and the NMOS transistor NM12 are coupled to the storage node N1.
The operation of conventional SRAM of semiconductor memory device having the structure as described above will be explained.
If the high level of the precharge signal PRE is applied to the gates of the precharge NMOS transistors NM1 and NM2, the NMOS transistors NM1 and NM2 should turned on so as to precharge the bit line BL and the inverted bit line /BL, respectively.
If the precharge signal PRE is "high" state, the NMOS transistor NM62 of the dummy bit line unit 60 is turned on so that the dummy bit line DUBL is precharged to "high" level and the inverted dummy bit line signal /S1, which is the output of the inverter IV62, becomes "low" level. In this condition, if any one of M word lines WL[M-1:0] is activated on "high" level, the corresponding NMOS transistor NM64, NM66 or NM68 is turned on so that the dummy bit line DUBL becomes "low" level and the inverted dummy bit line signal /S1 (that is the output of the inverter IV62) becomes "high" level.
In the read operation of the data stored in the memory cell 10, the sense amplifier 20 is activated by the high level of sense enable signal SE, so as to sense and amplify the difference in voltages between the storage node N1 and the storage node N2, through the bit line BL and the inverted bit line /BL, and then produce its result through the output node DOUT.
In the write operation of the data to the storage nodes N1 and N2 of the memory cell 10, the NMOS transistor NM7 is turned on by the high level of the internal write signal WR applied to the gate thereof, so that the data bus line DBL is electrically coupled to the output of the CMOS inverter 40. In addition, the NMOS transistor NM5 is turned on by the high level of the column signal COL so that the data bus line DBL and the bit line BL is electrically coupled to each other. The access transistors NM13 and NM14 are also turned by the high level of word line signal. Accordingly, the output data of the CMOS inverter 40 is transferred to the storage node N1 through the NMOS transistor NM7, the data bus line DBL, the NMOS transistor NM5, the bit line BL and the access NMOS transistor NM13. Similarly, the NMOS transistor NM8 is turned on by the high level of the internal write signal WR which is applied to the gate thereof, so that the output of the CMOS transistor 30 is electrically coupled to the inverted data bus line /DBL. In addition, the NMOS transistors NM6 and NM14 are turned due to the high level of the column signal COL and the word line signal, respectively, so that the inverted data bus line /DBL, the inverted bit line /BL and the storage node N2 are electrically coupled to one other. Accordingly the output data of the CMOS inverter 30 is transferred to the storage node N2 through the NMOS transistor NM8, the inverted data bus line /DBL, the NMOS transistor NM6, the inverted bit line /BL and the NMOS transistor NM14. Thus, the data of the storage nodes N1 and that of storage node N2 are different from each other.
In other words, when the CMOS inverter 30 receives the low level of data signal DIN, the storage node N1 stores a low level of data, while the storage node N2 stores a high level of data. In contrast, when the CMOS inverter 30 receives the high level of data signal DIN, the storage node N1 stores a "high" level data and the storage node N2 stores a "low" level data.
FIG. 2 illustrates a conventional control circuit for controlling the write operation of SRAM of the semiconductor memory device as described in FIG. 1.
Referring to FIG. 2, the conventional control circuit for semiconductor memory device comprises an address transition detector 50, an inverter IV1 and a NOR gate NR1. The address transition detector 50 detects the transition of the address signal AD[N-1:0] which is applied to the input thereof and produces a precharge signal PRE which is for precharging the bit line BL and the inverted bit line /BL. The inverter IV1 receives the write enable signal /WE, which can be externally applied thereto, so as to produce a write signal WR. The NOR gate NR1 receives the inverted dummy bit line signal /S1 and the output of the NOR gate NR2 and performs NOR-operation thereon to produce the result of NOR-operation.
In addition, the conventional control circuit for semiconductor memory device further comprises a NOR gate NR2 and an inverter IV2. The NOR gate NR2 receives and performs NOR-operation on the output signal of the address transition detector 50, the output signal of the inverter IV1 and the output signal of the NOR gate NR1 and produces the NOR-operation result as an X-decoder (not shown) enable signal XDEC_ENB which is used for making enable an X-decoder(not shown) for receiving and decoding X-address of the memory. This X-decoder enable signal XDEC_ENB is buffered by a buffer 70. The inverter IV2 inverts the X-decoder enable signal XDEC_ENB to produce a sense enable signal SE which is for activating the sense amplifier 20 of FIG. 1. Here, the buffer 70 includes even number of inverters IV3 and IV4. Here, the prefix "/" or the suffix "B" of a reference character for signal represent that the signal is a low active signal.
In addition, the word line signal generator receives the address signal AD[N-1:0] and the X-decoder enable signal XDEC_ENB and produces a plurality of word line signals WL[M-1:0]. When the X-decoder enable signal XDEC_ENB is "0" (that is, "low" level), any one of M word lines is selectively activated to "high" level. Alternatively, when the X-decoder disable signal is "1" (that is, "high" level), all of the word line WL[M-1:0] are disabled to "low" level.
FIGS. 3A and 3B illustrate the waveforms of the signals of FIG. 2, during read operation and write operation, respectively.
The operation of the conventional control circuit for semiconductor memory device will be explained during read operation, with reference to FIG. 3A.
In FIGS. 3A and 3B, reference character /WE, AD, PRE, XDEC.sub.13 ENB, SE, WL and /S1 represent the write enable signal, the address signal, the precharge signal, X-decoder enable signal, the sense enable signal, word line signal and the dummy bit line signal, respectively.
Referring to FIG. 3A, when any bit of multiple bits of the address signal AD makes the transition from high to low or the transition from low to high, the address transition detector 50 produces a high level of precharge signal PRE which has a predetermined pulse duration. That is, the precharge signal PRE makes the transition from high level to low level after the predetermined time elapses. Then, the precharge signal PRE from the address transition detector 50 maintains a low level until the address signal AD makes again any transition.
Subsequently, when the address transition detector 50 produces a high level signal, the dummy bit line unit 60 produces a low level of the inverted dummy bit line signal /S1 to the NOR gate NR1. The NOR gate NR2 produces a low level signal feedback to the NOR gate NR1 in response to the high level of the precharge signal PRE, so that the NOR gate NR1 produces a high level signal.
Here, the output node Y of the NOR gate NR2 and the output node X of the NOR gate NR1 continuously maintain their level even after the precharge signal PRE returns to the low level.
Thus, during the high duration of the precharge signal, the X-decoder enable signal XDEC_ENB from the buffer 70 is "low" level and the sense enable signal SE from the inverter IV2 is "high" level.
Then, while the X-decoder enable signal XDEC_ENB is low, a word line signal WL selected in response to the address signals AD [N-1:0] makes the transition from low level to high level, which turns on the access NMOS transistors NM13 and NM14 of one selected memory cell 10. Thus, the potentials of the bit line BL and the inverted bit line /BL is developed according to the data of the selected memory cell and then amplified by the sense amplifier 20. The amplified data is transferred to the data output DOUT. The selected word line WL is "high", so that the inverted dummy bit line signal /S1 becomes "high" level. In response to the high state of the inverted dummy bit line signal /S1, the X-decoder enable signal XDEC_ENB becomes "high" level and the sense enable signal SE becomes "low" level. Then, due to the "high" level of X-decoder enable signal XDEC_ENB, all word line signal WL become "low" and the inverted dummy bit line signal /S1 also becomes "low" level.
In the read operation as described above, the needless power consumption is reduced by automatically turning off the sense amplifier 20 and by making the word line "low" level, after data reading from the selected memory cell, even though the duration of the address signal is unduly long maintained.
The write operation of the semiconductor memory device will be explained, with reference to FIG. 3B.
The inverter IV1 produces a high level of write signal WR, when a low level of the write enable signal /WE is externally applied thereto. Then, the buffer 70 produces a low level of X-decoder enable signal XDEC_ENB and the inverter IV2 produces a high level of sense enable signal SE. In other words, when the write enable signal /WE is "low", the X-decoder enable signal is always "low" irrespective of the precharge signal and the inverted dummy bit line signal /S1. Thus, as the write enable signal /WE, which is externally applied, is unduly long, the sense amplifier and the X-decoder are activated during unduly lengthen period, thereby increasing the power consumption.
On the other hand, when the data stored in the cell is "0" (or a "low" level) and the data to be written is "1" (or a "high" level), the current path is made from the power source VDD to the ground VSS through the static precharge NMOS transistor NM4, the inverted bit line /BL and the NMOS transistors NM6, NM8 and NM9, with needless power consumption. Also, since the internal write signal WR is not affected by the precharge signal PRE, when the external write enable signal /WE is "low" level and the precharge signal PRE is "high" level, the current through the NMOS transistors NM1 and NM2 is selectively passed to the following paths, in accordance with the data to be written: one path is composed of 3 NMOS transistors NM5, NM7 and NM10 and the other path is composed of 3 NMOS transistors NM6, NM8 and NM9. As a result, power is needlessly consumed.
In addition, during the "low" state of the write enable signal /WE, since the sense enable signal SE is "high", the sense amplifier is continuously activated even after data outputting, with needless power consumption.
As a result, as the duration of the "low" level of the write enable signal /WE in write operation is long, the internal write signal WR, which is affected only by the write enable signal /WE, should be maintained "high" level. Such unduly long "high" level duration of the write signal results in undesirable power consumption.
Therefore, the above conventional control circuit for semiconductor memory device requires the much current to be driven, so that it makes the much power consumption. Thus there is a problem that the above control circuit is difficult to be applied to a small electronic product such as a portable electronic product.